Logic circuits implemented on an integrated circuit are typically synchronized by distributing a master clock signal to each timing critical circuit. The transfer of data in a clocked system, such as a microprocessor, is generally controlled by a master clock. The successful operation of a microprocessor, in large part, relies on the accuracy and performance of the master clock.
When testing semiconductor devices, the master clock is often provided by the automatic test equipment (ATE), which drives precisely timed signals to, and compares signals from, the pins of the device to test for acceptable device operation. The ATE master clock also provides a reference for the ATE timing circuitry to ensure that data signals from the ATE arrive at the DUT pins in a synchronized manner within acceptable limits.
While the microprocessor under test is but one device, the ATE to test it has duplicate electronic circuit resources, or channels, associated with each device pin. Thus, for each pin of the microprocessor being tested, there may be several integrated circuits employed for the ATE timing circuitry, pattern generation circuitry, waveform formatting circuitry, and so forth. Distributing a master clock to each of the ATE integrated circuits is no small problem.
With microprocessor operating frequencies surpassing one gigahertz, distributing the master clock within the ATE circuitry, and minimizing loss of accuracy has proved problematic. Additionally, modern microprocessors often employ circuitry responsive to data signals of varying frequencies.
One approach to distributing a high-speed and high-accuracy clock within a tester is to create the clock centrally. An expensive, highly accurate hardware module could be created or purchased to provide such a clock. Unfortunately, distribution of such a clock is problematic due to skew and jitter effects for each re-powering, and control problems with amplitude and skew. Moreover, a centralized single clock system fails to address the unique problems associated with devices having different pins receiving and transmitting different frequency signals.
A similar approach to the centrally created clocking scheme described above is employed in the Catalyst mixed-signal semiconductor test system, manufactured by Teradyne, Inc., in Boston, Mass. The scheme is shown generally in FIG. 1, and includes a digital master clock 8 distributed, or fanned out, to a plurality of digital and analog channel cards 10 and 12. Signals generated by a centralized pattern generator 14 are also fanned out with the digital master clock to the channel cards. The clock signals for the digital cards are fed to timing circuitry 16, which drives waveform formatting circuitry 18 to produce digital signals for application to the device-under-test (DUT, not shown). The analog cards 12, on the other hand, receive the remotely generated digital master clock signal, and synthesize it through an analog clock module (ACM) 19, to produce a local analog sinusoidal waveform A0 used to drive one or more analog instruments. One form of the analog clock is described in U.S. Pat. No. 6,188,253, entitled Analog Clock Module, assigned to the assignee of the present invention, and expressly incorporated herein by reference.
While this scheme is beneficial for its intended applications, the practical limitation to the fanning-out of the digital master clock to the digital boards is around 500 Mhz. At higher clock frequencies, jitter becomes more pronounced, degrading the accuracy of the tester. This problem is less pronounced for the analog boards because the analog clock is created locally on the board.
Therefore, a need exists in the art for an inexpensive clock architecture that distributes a digital clock signal with high accuracy throughout a tester to generate a high-frequency digital clock for the digital channel cards. The clock architecture of the present invention satisfies this need.